Digital data streams in wire-linked communication systems, such as Ethernet, FireWire, and other serial communication networks, are usually transmitted without an accompanying clock circuit. As such, a clock and data recovery (CDR) circuit is typically used by a receiver of the system to synchronously process the data, which ensures a recovered clock to be properly aligned to the incoming data.
A CDR circuit attempts to recover the clock and data by utilizing a digital filter and a phase interpolator. The digital filter estimates the phase position of upcoming level transitions in a serial data signal; and the phase interpolator controls sampling to occur at an optimal time. The digital filter resembles a feedback control loop that examines the sign of the phase error between the currently recovered clock and the data. If the recovered clock is too early, the phase interpolator delays the clock. If the recovered clock is too late, the phase interpolator advances the clock. A conventional digital loop filter is either a first order filter or a second order filter, which cannot completely cancel the residual jitter of the system, especially when the receiver clock is originally generated based on spread-spectrum. As such, existing CDR circuits are not entirely satisfactory in terms of performance and stability.